It is well known to use transistors within mixers and amplifiers. If the transistor was perfectly linear, such that, for example, current flowing through the transistor was linearly proportional to a voltage at the gate of the transistor where the transistor is a field effect transistor, or was proportional to the voltage at the base of the transistor, where the transistor is a bi-polar transistor, then high performance amplifier design would be much simplified. However, in reality, transistors exhibit non-linearities in their transfer characteristic and this can give rise to the generation of harmonic components, even when amplifying an AC signal having a monotonic frequency F1.
The reduction or elimination of harmonics is particularly important within the telecommunications industry. Non-linearities in amplifiers or mixers may result in transmissions outside of a nominal transmission frequency band having power levels in excess of those permitted by the licensing authorities. Similarly, the generation of harmonic signals or mixing of signals (such as inter-modulating of interfering signals) within a receiver due to non-linearities could degrade reception of a desired signal.
The consumer's desire for portable and feature rich mobile telephones has led to a high degree of integration of circuits within the telephone, and frequently transistor amplifiers are fabricated within integrated circuits used in the telephones and other telecommunications equipment. Integrated circuit fabrication techniques have the advantage that transistors within an integrated circuit can be matched to one another with a high degree of precision, especially when the transistors are physically close to one another within the integrated circuit. Process variations and other variables mean that the absolute performance characteristics of the transistors will not be known and that from one integrated circuit to the next the characteristics of any given transistor within the integrated circuit may vary.
FIG. 1 schematically illustrates a simplified field effect amplifier circuit. The field effect transistor 2 has a gate terminal 4 which receives a bias voltage from a bias voltage generator 6 via a resistor 7. The gate terminal 4 also receives an input signal which is to be amplified. A DC blocking capacitor 8 has been provided such that the circuit providing the input signal does not perturb the biasing arrangement of the transistor 2. The transistor has a drain terminal which is connected to a positive supply rail via a load impedance 10 which, for simplicity, has been illustrated as being a resistor. A source terminal of the transistor is connected to ground in this example.
The response characteristics of field effect transistors are summarised in many textbooks. FIGS. 2a and 2b show the response characteristics of a 3N163 P-channel MOSFET, as reproduced on page 245 of “microelectronics: Digital and Analog Circuits and Systems”, by Jacob Millman (ISBN 0-07-Y66410-2).
This text book repeats a theoretical analysis of the transfer characteristic, as suggested that
  Id  =                    μ        ⁢                                  ⁢                  C          O                ⁢        W                    2        ⁢                                  ⁢        L              ⁡          [                        2          ⁢                      (                                          V                GS                            -                              V                T                                      )                    ⁢                      V            DS                          -                  V          DS          2                    ]      
Where μ=majority carrier mobility                CO=gate capacitance per unit area        L=channel length        W=channel widthwith this simplifying to the current being proportional to the square of |VGS−VT| in the saturation region.        
However the values measured for real transistors vary from the ideal, as shown in FIG. 2b. In fact, although not clear from FIG. 2b, in a modern MOSFET within an integrated circuit there is a relatively significant amount of sub-threshold (VGS<Vt) conduction. Then after VGS is reached a square law like behaviour is found, but as the voltage increases this behaviour starts to fail as the field related effects become more significant.
In reality, the transistor's characteristic is not linear and this can be shown by looking at the derivatives of the change in drain to source current IDS as a function of the change in the gate source voltage.
It should be noted that the current IDS flowing through the transistor is a function of both the gate source voltage and the drain source voltage. Assuming that the transistor is only “weakly” non-linear, then it is generally acceptable to write its characteristic using a Taylor series, as set out in “Linearity Analysis of CMOS for RF Applications” Kant et al, IEEE Transactions on Microwave Theory and Techniques, March 2003. Thus, we can write:
                                          i            ds                    ⁡                      (                                                            V                  GS                                +                                  v                  gs                                            ,                                                V                  DS                                +                                  v                  ds                                                      )                          =                                            I              DS                        ⁡                          (                                                V                  GS                                ,                                  V                  DS                                            )                                +                                    G              m                        ·                          v              gs                                +                                    G              d                        ·                          v              ds                                +                                    G                              m                ⁢                                                                  ⁢                2                                      ·                          v              gs              2                                +                                    G              md                        ·                          v              gs                        ·                          v              ds                                +                                    G                              d                ⁢                                                                  ⁢                2                                      ·                          v              ds              2                                +                                    G                              m                ⁢                                                                  ⁢                3                                      ·                          v              gs              3                                +                                    G                              m                ⁢                                                                  ⁢                2                ⁢                                                                  ⁢                d                                      ·                          v              gs              2                        ·                          v              ds                                +                                    G                              md                ⁢                                                                  ⁢                2                                      ·                          v              gs                        ·                          v              ds              2                                +                                    G                              d                ⁢                                                                  ⁢                3                                      ·                          v              ds              3                                +          …                                    Equation        ⁢                                  ⁢        1            where                ids=change in Drain-Source current        VGS=gate-source voltage        vgs=change in gate-source voltage        VDS=drain-source voltage        vds=change in drain source voltage        IDS(VGS, VDS) is the bias current a the nominal gate-source voltage VGS and the drain-source voltage VDS         Gm=coefficient of transconductance        Gd=coefficient        Gm2=coefficient        Gd2=coefficient        Gm3=coefficient        Gm2d=coefficient        
If the drain is effectively shorted from the point of view of AC signals, i.e. a cascode transistor is provided, then the output conductance and cross modulation terms (e.g. those terms which are a function of Vds, Vds2 etc) can be largely ignored. Furthermore, if we concentrate only on the lower order terms, because the higher order coefficients tend to be very small, then the expression can be simplified and some substitutions made to yieldg(VGS+vgs)≈+Gm+2·Gm2·vgs+3·Gm3·vgs2  Equation 2where, comparing terms we see                g(VGS+Vgs) represents the incremental transconductance, i.e. the expansion of        
      ⅆ          I      DS            ⅆ          V      GS      around the DC bias point VGS                 g(VGS)≈Gm−proportional to        
      ⅆ          I      DS            ⅆ          V      GS      g(VGS+ΔV)≈Gm+2·Gm2·ΔV+3·Gm3·ΔV2g(VGS−ΔV)≈Gm−2·Gm2·ΔV+3·Gm3·ΔV2therefore
            G      m        =          g      ⁡              (                  V          GS                )                        G              m        ⁢                                  ⁢        2              =                            g          ⁡                      (                                          V                GS                            +                              Δ                ⁢                                                                  ⁢                V                                      )                          -                  g          ⁡                      (                                          V                GS                            -                              Δ                ⁢                                                                  ⁢                V                                      )                                                4          ·          Δ                ⁢                                  ⁢        V                        G              m        ⁢                                  ⁢        3              =                            g          ⁡                      (                                          V                GS                            +                              Δ                ⁢                                                                  ⁢                V                                      )                          +                  g          ⁡                      (                                          V                GS                            -                              Δ                ⁢                                                                  ⁢                V                                      )                          -                  2          ·                      g            ⁡                          (                              V                GS                            )                                                            6          ·          Δ                ⁢                                  ⁢                  V          2                    
FIGS. 3a to 3c show the values Gm1, Gm2 and Gm3 for a typical field effect transistor over a range of gate to source voltages. Thus, FIG. 3a shows
            ⅆ              I        DS                    ⅆ              V        GS              .FIG. 3b shows the second order
            ⅆ      2        ⁢          I      DS            ⅆ          V      GS      2      derivative and FIG. 3c shows the third order derivative
                    ⅆ        3            ⁢              I        DS                    ⅆ              V        GS        3              .It can be seen that there is a bias voltage, VGS where the third order derivative falls to zero. In this example it occurs at VGS=0.6 volts. Therefore, for the transistor to which these characteristic curves relate, if that transistor had a gate source bias of 0.6 volts then it would exhibit substantially no third order non-linearity and as a result would tend not to generate third order harmonics. Similarly third order inter-modulation of, for example, interfering signals within an RF front end, would also be minimised.
Unfortunately, it can also be seen that the gradient of the line shown in FIG. 3c is very steep around this zero intercept point and hence any deviation away from the ideal position quickly introduces a significant amount of third order non-linearity. Furthermore, if the characteristics of the circuit vary from circuit to integrated circuit within the same batch and from wafer to wafer within different batches it is not sufficient or desirable merely to set up the same bias voltage for all instances of this circuit because only a very small proportion of them are likely to be biased anywhere near the correct bias conditions and a large proportion of the circuits are biased at a point where they give rise to quite pronounced third order non-linearities.
It is therefore desirable to characterise each transistor individually and bias it to an appropriate point.
In practical terms it would be very time consuming to characterise each instance of an amplifier that was fabricated, especially as the bias point may change with temperature and age.
Other workers in this field have attempted to address the problem by actively calculating the value of Gm3. It is well known that in order to numerically calculate the first order derivative of a parameter, it is necessary to compare the value at at least two distinct points. Similarly, to calculate the second order derivative it is necessary to compare the values of at least three points and it is well known, as illustrated in FIG. 4, that to numerically calculate the third order derivative it is necessary to examine the values at four points (or more) along the curve.
In the context of the present invention, this means making slight perturbations to the gate voltages of four closely scaled or eight matched transistors and comparing the currents flowing therethrough. A circuit for doing this is shown in FIG. 5 and was described in U.S. Pat. No. 6,531,924.
In essence this circuit uses a string of resistors to generate four input voltages centred around the bias voltage for the transistor amplifier. Four comparison transistors then pass currents as a function of the bias voltage and these currents are summed by an operational amplifier to give a value representative of the third order derivative. Critically this circuit requires the performance of the four transistors to be accurately matched, even though two of them are required to pass three times as much current (and hence can be formed by three transistors in parallel) as the other two. Thus this circuit can be expected to consume eight times as much current as the actual amplifier it represents if the transistor and currents are the same as in the amplifier. It is possible to scale the transistors used an the currents that they pass so as to reduce the current drawn, but this reduces the matching between the amplifier and the derivative calculating circuit. Any mismatch will give rise to an error in the result. It is suspected that whilst this circuit looks good in theory there will be a trade off between matching and power consumption which may make implementation difficult in system having a tight power budget.